1) Field of the Invention
The present invention relates to a circuit designing apparatus of an interactive type which conducts a circuit design of an integrated circuit such as an LSI or a printed circuit board in an interactive form while displaying steps of the circuit design on a display unit such as a display or the like.
2) Description of the Related Art
In general, a logic design, a layout design (a mounting design) or a speed analysis are conducted when a circuit such as an LSI, a printed board, etc. is designed.
More specifically, a logic design for realizing functions demanded by a circuit that is an object of the design is first conducted. A layout design for determining a placement in mounting (physical) of cells (sometimes called elements or gates) such as flip-flops as logic components or wiring between the cells is then conducted on the basis of a result of the logic design.
After the layout design, a speed analysis on the basis of a delay computation is conducted for each path obtained as a result of the design to feed-back a magnitude of a delay obtained as a result of the analysis. The logic design and the layout design are again performed in order to improve a delay of each path. The above logic design, layout design and speed analysis are repeated by trial-and-error until each path has an optimum delay.
A system (a software) for conducting a logic design, a layout design and a speed analysis in each step has been existing as an interactive logic design system, an interactive layout design system and an interactive speed analysis system, which are not in a system structure suitable for conducting processes in linkage. For this, a circuit design is conducted in a series of processes accompanied by feed-back in the known technique.
In the general circuit designing technique set forth above, the logic design, the layout design and the speed analysis are not linked to each other since they are conducted separately by different systems (softwares). It is thus necessary to repeat each process sequentially, which causes a longer turnaround time and prevents a high-speed design and development of a circuit such as an LSI, a printed circuit board, etc.
There has been proposed a circuit designing apparatus of an interactive type in which a logic design system, a layout design system and a speed analysis system are connected so as to be able to link with each other on occasion.
However, even the circuit designing system of an interactive type in which each of the above systems exist separately or the circuit designing system of an interactive type in which the above systems are connected so as to be associated with each other results in the following various problems.
(1) Recently, integrated circuits such as LSI circuits, have become more microscopic. With this, a problem of a wiring capacitance becomes significant such that a waveform of a signal transferred in a wiring path on a circuit is apt to becomes rounded.
A binary signal transferred in a circuit rises or falls from one level to another within an extremely short time of about zero in theory. However, if a wiring capacitance increases as stated above, a slew rate of a rise or a fall from one level to another level increases. This slew rate is a measure of in a signal waveform. If rounding occurs, a time (Tsin) required to reach from one level to another level increases, thus a time required to reach a threshold value used to judge as to whether the binary signal is in either one of two levels, as a matter of fact. If a delay value in the event that a signal having such rounding passes through a logic component (referred as a gate, cell or element on occasion) is determined uniformly upon speed analysis as before, a difference between a calculated delay value and an actual delay value becomes extremely large, which prevents an accurate delay computation.
(2) A delay computation by speed analysis is conducted after placement of logic components or after wiring between placed components, in general. There has been no case where the delay computation is conducted in a stage after a logic design. As a circuit that is an object of a design becomes more microscopic and highly integrated, there is a demand to obtain a result of a delay computation in an early stage, that is, a final stage of a logic design so as to take it into account in the design.
(3) In a wiring design of an integrated circuit such as an LSI or the like, data transfer between flip-flops (FFs) that are logic components should meet various timing restrictions (overdelay, racing). It is impossible for the designer to pay attention to wiring paths of all combinations of flip-flops of the number extending, in general, to hundreds of thousands to make a check as to whether a result of the wiring design meets the timing restrictions in any of the above circuit designing apparatus of an interactive type.
(4) If a condition of wiring connections of a circuit that is an object of the design is displayed on a display unit such as a display in a wiring design of an integrated circuit such as an LSI or the like, each of characteristic points for the wiring (vias, pins of logic components, or the like) is displayed in a displaying position proportional to actual coordinate values of the characteristic point. In this case, if there is a large difference in density of existing characteristic points locally, it is difficult to discriminate a detailed part having a high density on the display unit if the whole of the circuit is displayed. If the detailed part is enlarged and displayed, it is difficult to grasp the whole image of the circuit that is the object of the design.
(5) If wiring between logic components is performed after each of the logic components has been placed in a layout design, a part in which a wiring is extremely congested or a part in which a tight restriction to a delay value (a high critical degree) set in advance is imposed on a wiring may occur depending on a condition of placement of the logic components. An actual wiring devoid of a consideration on such parts causes a lot of unroutable parts and degradation of wiring efficiency.
(6) Cell that is a logic component placed on an integrated circuit such as an LSI or the like has been in the same shape and the same size. Once a placing position for a cell is determined, there has occurred no placement error such as cell overlapping or the like. However, there is a case where cells having different sizes are placed on the same circuit with a change in the LSI technology, a placement error such that cells overlap to each other may occur. In the present condition, there is no way for the designer to immediately know such placement error. For this, there is a demand for a development of a technique helpful for the designer to clearly know a condition of occurrence of a placement error.
(7) If a part that has been already wired is rewired, the designer designates two points that should be re-wired on a wiring path that has been wired, and conducts a re-wiring in a designated wiring length, which imposes a great burden on the designer. In consequence, there is a demand for a simplified, automated re-wiring process.
(8) In the case of replacing a cell that has been placed, a re-wiring of the cell after the re-placement cannot be executed unless the designer gives an instruction to re-wire separately even if a net that should be linked to the cell has been wired, which imposes a great burden on the designer. There is therefore a demand for a simplified, automated re-placing process.
(9) While plural placement maps of a common circuit are displayed on the display unit, the designer refers to one of these maps and conducts a placing process or a wiring process on the map. However, a result of the process does not reflect on other maps. As a result, there occurs a case where a result of an alteration in design differs from a condition of the design displayed on the placement map, which may cause a confusion of the designer who works out a design in an interactive form by referring the display unit.
(10) With an increase of the number of elements mounted on an integrated circuit such as an LSI or the like, a technique for dividing an inside of the chip into plural hierarchical layout blocks (LSG: Layout Sub-Group) to conduct a mounting becomes the main current. At this time, a net connecting divided blocks exists, in general. Therefore, in a hierarchical layout design, an input/output terminal (a virtual block terminal; referred as a temporary terminal, hereinafter) is temporarily provided to each block, the temporary terminal is placed at the time of placement of the inside of each block, an element and the temporary terminal are connected inside the block, and the temporary terminals of respective blocks are wired and connected to connect the blocks.
Upon the hierarchical layout design as above, it is necessary that a temporary terminal is manually placed by the designer in a place that the designer thinks appropriate in consideration of a connection of the temporary terminal and an element in the block or a connection of the temporary terminal and another block. A recent layout design system employs a technique for automatically placing all blocks in consideration on a relation of placement of individual blocks in the entire circuit. However, a manual work including a shift of each temporary terminal is indispensable in order to conduct a placement respecting an intention of the designer. Since this process is conducted in consideration of only placement of blocks, no attention is paid regarding placement of elements inside the block or wiring between the elements.
(11) An input/output terminal of an integrated circuit such as an LSI or the like is placed in a peripheral area of the chip. There has been no freedom to alter its coordinates in a mounting design. To the contrary, by employing a technique for arranging spherical terminals called bumps on the chip surface, it is possible to determine a position of the input/output terminal on the chip, which increases a degree of freedom in placement. With this, it becomes possible to place an input/output circuit that should be connected to the input/output terminal within a region in which a general element is placed close to a position of the input/output terminal.
An increase of a degree of freedom to place the input/output terminal and the input/output circuit sometimes causes a limitation of in wiring length between the input/output terminal and the input/output circuit. In the case of the hierarchical layout design stated above, there is a possibility that the input/output terminal and the input/output circuit belong different layout hierarchical blocks. In such a case, there is no way to examine when an inside of each block is being designed as to whether the wiring length between the input/output terminal and the input/output circuit is below the limit value. Or, there is a possibility that a region in which the input/output circuit should be placed is not definite since a placing position of the input/output terminal is not definite.